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1. general description the tda19977a; TDA19977B is a three i nput hdmi 1.4a compli ant receiver with embedded edid memory. the built-in auto-ad aptive equalizer, improves signal quality and allows the use of cable lengths of up to 25 m which are laboratory tested with a 0.5 mm (24 awg) cable at 2.05 gigasamples per second. the hdcp (tda19977a only) key set is stored in non-volatile otp (one time programmable) memory for maximum security. in addition, the tda19977a; tda19 977b is delivered with software drivers to ease configuration and use. the tda19977a; TDA19977B supports: ? tv resolutions: ? 480i (1440 480i at 60 hz), 576i (1440 576i at 50 hz) to hdtv (up to 1920 1080p at 50/60 hz) ? wuxga (1920 1200p at 60 hz) reduced blanking format ? pc resolutions: ? vga (640 480p at 60 hz) to uxga (1600 1200p at 60 hz) ? deep color mode in 10-bit and 12-bit (up to 205 mhz tmds clock) ? gamut boundary description ? iec 60958/iec 61937, oba (one bit audio), dst (direct stream transfer) and hbr (high bit rate) stream the tda19977a; TDA19977B includes: ? an enhanced pc and tv format recognition system ? generation of a 128/256/512 f s system clock allowing the us e of simple audio dacs without an integrated pll (such as the uda1334bts) ? an embedded oscillator (an external crystal can also be used) ? improved audio clock generation us ing an external reference clock ? oba (as used in sacd), dst and hbr stream support the tda19977a; TDA19977B converts hdmi streams with or without hdcp (tda19977a only) into rgb or ycbcr digital signals. the ycbcr digital output signal can be 4:4:4 or 4:2:2 semi-planar format based on the itu-r bt.601 standard or 4:2:2 based on the itu-r bt.656 format. the device can adju st the output timing of the video port by altering the values of t su(q) and t h(q) . in addition, all settings are controllable using the i 2 c-bus. tda19977a; TDA19977B triple input hdmi 1.4a complia nt receiver interface with equalizer (up to 1080p for hd tv, and uxga for pc formats rev. 3 ? 19 november 2010 product data sheet www.datasheet.in
tda19977a_TDA19977B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserv ed. product data sheet rev. 3 ? 19 november 2010 2 of 40 nxp semiconductors tda19977a; TDA19977B triple input hdmi receiver interface with digital processing 2. features and benefits ? complies with the hdmi 1. 4a, dvi 1.0, cea-861-d and hdcp (tda19977a only) 1.4 standards ? three independent hdmi inputs, up to the hdmi frequency of 205 mhz ? embedded auto-adaptive equalizer on all hdmi links ? edid memory: 253 shared bytes and three bytes dedicated to each hdmi input ? supports color depth processing (8-bit, 10-bit or 12-bit per color) ? color gamut metadata packet with interrupt on each update, readable via the i 2 c-bus ? up to four s/pdif or i 2 s-bus outputs (eight channels) at a sampling rate up to 192 khz with iec 60958/iec 61937 stream ? hbr audio stream up to 768 khz with four demultiplexed s/pdif or i 2 s-bus outputs ? hbr streams (compatible with dts-hd master audio and dolby truehd up to eight channels due to hbr packet for stream with a frame rate up to 768 khz) support ? dsd and dst audio stream up to six dsd channels output for sacd with dst audio packet support ? channel status decoder supports multi-channel reception ? improved audio clock generation us ing an external reference clock ? system/master clock output (128/256/512 f s ) enables the use of the uda1334bts ? the hdmi interface supports: ? all hdtv formats up to 1920 1080p at 50/60 hz and wuxga (1920 1200p at 60 hz) with support for reduced blanking ? 3d formats including all primary formats up to 1920 1080p at 30 hz frame packing and 1920 1080p at 60 hz top-and-bottom ? pc formats up to uxga (1600 1200p at 60 hz) ? embedded oscillator (an exte rnal crystal can be used) ? frame and field detection for interlaced video signal ? sync timing measurements for format recognition ? improved system for measurements of blanking and video active area allowing an accurate recognition of pc and tv formats ? hdcp (tda19977a only) wit h repeater capability ? embedded non-volatile memory storage of hdcp (tda19977a only) keys ? programmable color space input signal conversion from rgb-to-ycbcr or ycbcr-to-rgb ? output formats: rgb 4:4:4, ycbcr 4:4:4, ycbcr 4:2:2 semi-planar based on the itu-r bt.601 standard and ycbcr 4:2:2 itu-r bt.656 ? 8-bit, 10-bit or 12-bit output formats selectable using the i 2 c-bus (8-bit and 10-bit only in 4:4:4 format) ? i 2 c-bus adjustable timing of video port (t su(q) and t h(q) ) ? downsampling-by-two with sele ctable filters on cb and cr channels in 4:2:2 mode ? internal video and audio pattern generator ? controllable using the i 2 c-bus; 5 v tolerant and bit rate up to 400 kbit/s ? ddc-bus inputs 5 v tolerant and bit rate up to 400 kbit/s ? lv-ttl outputs ? power-down mode ? cmos process www.datasheet.in
tda19977a_TDA19977B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserv ed. product data sheet rev. 3 ? 19 november 2010 3 of 40 nxp semiconductors tda19977a; TDA19977B triple input hdmi receiver interface with digital processing ? 1.8 v and 3.3 v power supplies ? lead-free (pb) hlqfp144 package 3. applications 4. quick reference data [1] x = a, b or c. [2] at 30 % activity on video port output. [3] hdcp decoding is only supported by the tda19977a. ? hdtv ? high-end tv ? ycbcr or rgb hi-speed video digitizer ? home theater amplifier ? projector, plasma and lcd tv ? dvd recorder ? rear projection tv ? avr and hdmi splitter table 1. quick reference data symbol parameter conditions min typ max unit digital inputs: pins rxxc+, rxxc ? [1] f clk(max) maximum clock frequency 205 - - mhz clock timing output: pins vclk, aclk and sysclk f clk(max) maximum clock frequency pin vclk 165 - - mhz pin aclk 25 - - mhz pin sysclk 50 - - mhz supplies v ddh(3v3) hdmi supply voltage (3.3 v) 3.135 3.3 3.465 v v ddh(1v8) hdmi supply voltage (1.8 v) 1.71 1.8 1.89 v v ddi(3v3) input supply voltage (3.3 v) 3.135 3.3 3.465 v v ddc(1v8) core supply voltage (1.8 v) 1.71 1.8 1.89 v v ddo(3v3) output supply voltage (3.3 v) 3.135 3.3 3.465 v p power dissipation active mode [2] 720p at 60 hz - 0.75 - w 1080p at 60 hz - 1.13 - w 1080p at 60 hz; deep color mode - 1.63 - w p cons power consumption power-down mode pin pd = high - 1 - mw i 2 c-bus; edid and hdcp [3] memory power-up -4-mw i 2 c-bus; edid; activity detection and hdcp [3] memory power-up - 150 - mw www.datasheet.in
tda19977a_TDA19977B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserv ed. product data sheet rev. 3 ? 19 november 2010 4 of 40 nxp semiconductors tda19977a; TDA19977B triple input hdmi receiver interface with digital processing 5. ordering information table 2. ordering information type number package name description version tda19977ahv hlqfp144 plastic thermal enhanced low profile quad flat package; 144 leads; body 20 20 1.4 mm; exposed die pad sot612-3 TDA19977Bhv hlqfp144 www.datasheet.in
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x tda19977a_TDA19977B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserv ed. product data sheet rev. 3 ? 19 november 2010 5 of 40 nxp semiconductors tda19977a; TDA19977B triple input hdmi receiver inte rface with digital processing 6. block diagram (1) only used by tda19977a. fig 1. block diagram of tda19977a; TDA19977B 001aai38 1 hdmi a (channels 0/1/2) hdmi a (channel a) xtalin/mclk xtalout ap4/ws ap0 to ap3 aclk vp[29:0] vclk sysclk/ap5 de hs/href vs/vref cs/fref rrx1 rrx2 sda/scl hsdaa/ hscla hsdab/ hsclb hsdac/ hsclc tda19977 sync timing measurement i 2 c-bus slave interface crystal oscillator termination resistance control hdmi b (channels 0/1/2) hdmi b (channel b) termination resistance control hdmi c (channels 0/1/2) hdmi c (channel c) termination resistance control edid memory otp (1) memory hdmi receiver and hdcp color depth unpacking video output formatter power management vhref timing generator audio fifo packet extraction audio pll audio formatter equalizer derepeater upsampler www.datasheet.in
tda19977a_TDA19977B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserv ed. product data sheet rev. 3 ? 19 november 2010 6 of 40 nxp semiconductors tda19977a; TDA19977B triple input hdmi receiver interface with digital processing 7. pinning information 7.1 pinning 7.2 pin description fig 2. pin configuration for tda19977a; TDA19977B tda19977 001aai38 2 108 37 72 144 109 73 1 36 table 3. pin description symbol pin type [1] description v ssc 1 g ground for the digital core pd 2 i power-down control input (active high) v ddh(3v3) 3 p hdmi receiver supply voltage; 3.3 v n.c. 4 i not connected n.c. 5 i not connected v ssh 6 g hdmi receiver ground rxcc ? 7 i hdmi input c negative clock channel rxcc+ 8 i hdmi input c positive clock channel v ddh(3v3) 9 p hdmi receiver supply voltage; 3.3 v n.c. 10 i not connected n.c. 11 i not connected v ssh 12 g hdmi receiver ground rxc0 ? 13 i hdmi input c negative data channel 0 rxc0+ 14 i hdmi input c positive data channel 0 v ddh(1v8) 15 p hdmi receiver supply voltage; 1.8 v n.c. 16 i not connected n.c. 17 i not connected v ssh 18 g hdmi receiver ground rxc1 ? 19 i hdmi input c negative data channel 1 rxc1+ 20 i hdmi input c positive data channel 1 v ddh(3v3) 21 p hdmi receiver supply voltage; 3.3 v n.c. 22 i not connected n.c. 23 i not connected www.datasheet.in
tda19977a_TDA19977B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserv ed. product data sheet rev. 3 ? 19 november 2010 7 of 40 nxp semiconductors tda19977a; TDA19977B triple input hdmi receiver interface with digital processing v ssh 24 g hdmi receiver ground rxc2 ? 25 i hdmi input c negative data channel 2 rxc2+ 26 i hdmi input c positive data channel 2 v pp 27 p otp memory programming voltage [2] v ddc(1v8) 28 p digital core supply voltage; 1.8 v v ddo(3v3) 29 p video port output supply voltage; 3.3 v vclk 30 o video clock output v sso 31 g video port output ground cs/fref 32 o composite synchronization output composite field output signal vs/vref 33 o vertical synchronization output vertical reference output hs/href 34 o horizontal synchronization output reference output de 35 o data enable output vp[0] 36 o video port output bit 0 v ssc 37 g digital core ground vp[1] 38 o video port output bit 1 vp[2] 39 o video port output bit 2 vp[3] 40 o video port output bit 3 v ddo(3v3) 41 p video port output supply voltage; 3.3 v v ddc(1v8) 42 p digital core supply voltage; 1.8 v v sso 43 g video port output ground vp[4] 44 o video port output bit 4 vp[5] 45 o video port output bit 5 vp[6] 46 o video port output bit 6 vp[7] 47 o video port output bit 7 vp[8] 48 o video port output bit 8 vp[9] 49 o video port output bit 9 vp[10] 50 o video port output bit 10 vp[11] 51 o video port output bit 11 v ddo(3v3) 52 p video port output supply voltage; 3.3 v vp[12] 53 o video port output bit 12 v sso 54 g video port output ground vp[13] 55 o video port output bit 13 vp[14] 56 o video port output bit 14 vp[15] 57 o video port output bit 15 vp[16] 58 o video port output bit 16 vp[17] 59 o video port output bit 17 vp[18] 60 o video port output bit 18 vp[19] 61 o video port output bit 19 table 3. pin description ?continued symbol pin type [1] description www.datasheet.in
tda19977a_TDA19977B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserv ed. product data sheet rev. 3 ? 19 november 2010 8 of 40 nxp semiconductors tda19977a; TDA19977B triple input hdmi receiver interface with digital processing vp[20] 62 o video port output bit 20 v ddo(3v3) 63 p video port output supply voltage; 3.3 v v ddc(1v8) 64 p digital core supply voltage; 1.8 v v sso 65 g video port output ground vp[21] 66 o video port output bit 21 vp[22] 67 o video port output bit 22 vp[23] 68 o video port output bit 23 vp[24] 69 o video port output bit 24 vp[25] 70 o video port output bit 25 vp[26] 71 o video port output bit 26 vp[27] 72 o video port output bit 27 v ssc 73 g digital core ground v ddo(3v3) 74 p video port output supply voltage; 3.3 v vp[28] 75 o video port output bit 28 vp[29] 76 o video port output bit 29 v sso 77 g video port output ground aclk 78 o audio clock output ap0 79 o audio port 0 output ap1 80 o audio port 1 output ap2 81 o audio port 2 output ap3 82 o audio port 3 output ap4/ws 83 o audio port 4 output word select output v ddo(3v3) 84 p video port output supply voltage; 3.3 v ap5/sysclk 85 o audio port 5 output system clock audio output v sso 86 g video port output ground v ddh(3v3) 87 p hdmi audio pll supply voltage; 3.3 v v ddh(3v3) 88 p hdmi audio pll supply voltage; 3.3 v v ssh 89 g hdmi audio pll ground v ddh(1v8) 90 p hdmi audio pll supply voltage; 1.8 v v ssh 91 g hdmi audio pll ground v ddc(1v8) 92 p digital core supply voltage; 1.8 v xtalout 93 o crystal oscillator output xtalin/mclk 94 i crystal oscillator input test pattern clock input v ddi(3v3) 95 p digital inputs supply voltage; 3.3 v vai 96 o video activity indication output (open-drain); warns the external microprocessor that a special event has occurred; must be connected to a pull-up resistor; 5 v tolerant (active low) sda 97 i/o i 2 c-bus serial data input/output table 3. pin description ?continued symbol pin type [1] description www.datasheet.in
tda19977a_TDA19977B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserv ed. product data sheet rev. 3 ? 19 november 2010 9 of 40 nxp semiconductors tda19977a; TDA19977B triple input hdmi receiver interface with digital processing scl 98 i i 2 c-bus serial clock input hsdaa 99 i/o hdmi input/output a (hdcp [3] ) ddc-bus serial data hscla 100 i hdmi input a (hdcp [3] ) ddc-bus serial clock hsdab 101 i/o hdmi input/output b (hdcp [3] ) ddc-bus serial data hsclb 102 i hdmi input b (hdcp [3] ) ddc-bus serial clock test0 103 i reserved for test; connect to digital inputs ground (v ssc ) v ddh(3v3) 104 p hdmi deep pll supply voltage; 3.3 v v ssh 105 g hdmi deep pll ground rrx1 106 i hdmi inputs a and b termination resistance control v ddc(1v8) 107 p digital core supply voltage; 1.8 v v ddh(1v8) 108 p hdmi receiver supply voltage; 1.8 v v ssc 109 g digital core ground a0 110 i i 2 c-bus address control input v ddh(3v3) 111 p hdmi receiver supply voltage; 3.3 v rxbc+ 112 i hdmi input b positive clock channel rxbc ? 113 i hdmi input b negative clock channel v ssh 114 g hdmi receiver ground rxac ? 115 i hdmi input a negative clock channel rxac+ 116 i hdmi input a positive clock channel v ddh(3v3) 117 p hdmi receiver supply voltage; 3.3 v rxb0+ 118 i hdmi input b positive data channel 0 rxb0 ? 119 i hdmi input b negative data channel 0 v ssh 120 g hdmi receiver ground rxa0 ? 121 i hdmi input a negative data channel 0 rxa0+ 122 i hdmi input a positive data channel 0 v ddh(1v8) 123 p hdmi receiver supply voltage; 1.8 v rxb1+ 124 i hdmi input b positive data channel 1 rxb1 ? 125 i hdmi input b negative data channel 1 v ssh 126 g hdmi receiver ground rxa1 ? 127 i hdmi input a negative data channel 1 rxa1+ 128 i hdmi input a positive data channel 1 v ddh(3v3) 129 p hdmi receiver supply voltage; 3.3 v rxb2+ 130 i hdmi input b positive data channel 2 rxb2 ? 131 i hdmi input b negative data channel 2 v ssh 132 g hdmi receiver ground rxa2 ? 133 i hdmi input a negative data channel 2 rxa2+ 134 i hdmi input a positive data channel 2 v ssh 135 g hdmi receiver ground v ddc(1v8) 136 p digital core supply voltage; 1.8 v v ddc(1v8) 137 p digital core supply voltage; 1.8 v hsdac 138 i/o hdmi input/output c (hdcp [3] ) ddc-bus serial data table 3. pin description ?continued symbol pin type [1] description www.datasheet.in
tda19977a_TDA19977B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserv ed. product data sheet rev. 3 ? 19 november 2010 10 of 40 nxp semiconductors tda19977a; TDA19977B triple input hdmi receiver interface with digital processing [1] p = power supply; g = ground; i = input; o = output and i/o = input/output. [2] connected to the ground of the hdmi receiver (v ssh ) in normal operation. [3] hdcp decoding is only supported by tda19977a. 8. functional description the tda19977a; TDA19977B converts digital data streams input by the hdmi sources into parallel digital data for use by media and video signal processing integrated circuits in devices for hdtv. data streams can be decoded with or without hdcp protection. outputs from the tda19977a; TDA19977B ca n be rgb 4:4:4, ycbcr 4:4:4, ycbcr 4:2:2 semi-planar format based on the itu-r bt.601 standard or ycbcr 4:2:2 based on the itu-r bt.656 format. inputs can be both progressive and interlaced formats. the tda19977a; TDA19977B comprises a color space conversion block, downsampling filters and an embedded timing code function. in addition, the hdcp (tda19977a only) repeater function enables other hdmi devices to be connected to form an extended ?total application?. 8.1 software drivers software drivers are provided for easy configuration and use of the tda19977a; TDA19977B. these drivers can be integrated with a large range of processors, with or without an operating system. they control acti vity detection, input selection, video mode identification, color conversion, power-down modes, hdcp (tda19977a only) and info frame notification. 8.2 hdmi inputs control of the three hdmi inputs can be automatic using activity detection or using the i 2 c-bus. the hdmi receiver inputs are defined by pins rxx0+, rxx0 ? , rxx1+, rxx1 ? , rxx2+, rxx2 ? , rxxc+, rxxc ? , rrxx, hsclx and hsdax. in the pin names, x equals a, b or c (as applicable). 8.3 termination resistance control the hdmi receiver input contains a terminati on resistance control set by an external resistor connected between pins rrxx and v ddh(3v3) . in rrxx, x equals 1 for inputs a and b or 2 for inputs c and d. typically, the characteristic impedance is 50 and the default value of the external te rminal control resistor is 12 k ? 1%. hsclc 139 i hdmi input c (hdcp [3] ) ddc-bus serial clock n.c. 140 i/o not connected n.c 141 i not connected v ddi(3v3) 142 p digital inputs supply voltage; 3.3 v rrx2 143 i hdmi inputs c and d termination resistance control v ddh(1v8) 144 p hdmi receiver supply voltage; 1.8 v exposed die pad - g exposed die pad; connect to digital core ground (v ssc ) table 3. pin description ?continued symbol pin type [1] description www.datasheet.in
tda19977a_TDA19977B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserv ed. product data sheet rev. 3 ? 19 november 2010 11 of 40 nxp semiconductors tda19977a; TDA19977B triple input hdmi receiver interface with digital processing 8.4 equalizer the auto-adaptive equalizer automatically measures and selects the settings which provide the best signal quality for each cabl e. this improves signal quality and enables the use of cable lengths up to 25 m (laboratory tested, contact nxp for detailed information). the equalizer is fully autom atic and consequently does not need any external control. 8.5 activity detection the tda19977a; TDA19977B uses activity detection to automatically select the active hdmi input. an internal, fully programmable, freq uency filter controls activity detection. it sees only the activity on the hdmi inputs with a frequency range between f min (22.5 mhz) and f max (205 mhz). this activity detection can generate an in terrupt enabling users to manage each hdmi input. 8.6 high-bandwidth digital cont ent protection (tda19977a only) the hdmi receiver also contains the hdcp decryption function. the keys provided by the otp non-volatile memory in encrypted format are decrypted and then stored in the hdcp module. this is particularly suitable for repeater applications. the tda19977a manages all hdcp repeater functions based on the hdcp 1.4 specification. three ddc-buses hscla/hsdaa; hsclb/ hsdab and hsclc/hsdac are integrated into the hdcp function, one bus for each hdmi input. the ddc-bus connected to the hdcp block is automatically selected based on the active hdmi input. the unused inputs are disconnected from the ddc-bus (no ackno wledge). no additional cpu processing is required because the authentication phase an d the re-key calculation are fully managed by the tda19977a. 8.7 color depth unpacking in deep color mode, the tda19977a; TDA19977B receives several fragments of a pixel group at the hdmi link frequency. this block tran slates the received pixel group into pixels at the pixel frequency. this operation is fu lly automatic and does not need any external control. 8.8 derepeater the hdmi source uses pixel repetition to increase the transmitted pixel clock for transmitting video formats at native pixel rates below 25 mpixel/s or to increase the number of audio sample packets in each line. the derepeater function discards repeated pixels and divides the clock to re produce the native video format. 8.9 upsample the hdmi source can use ycbcr 4:2:2 pixel encoding which enables the number of bits allocated per component to be increased up to 12. the upsample function transforms this 12-bit ycbcr 4:2:2 data stream into a 12-bit ycbcr 4:4:4 data stream by repeating or linearly interpolating the chrominance pixels cb and cr. upsampling mode is selected using the i 2 c-bus. www.datasheet.in
tda19977a_TDA19977B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserv ed. product data sheet rev. 3 ? 19 november 2010 12 of 40 nxp semiconductors tda19977a; TDA19977B triple input hdmi receiver interface with digital processing 8.10 packet extraction information sent during the data island peri ods are extracted from the hdmi data stream. audio clock regeneration, general control and info frames can be read using the i 2 c-bus while audio samples are sent to the audio fifo. the tda19977a; TDA19977B can receive the new hdmi 1.4a packets, general control and color gamut metadata information packets. in audio applications, the tda19977a; td a19977b manages hbr packets for high bit rate compressed audio streams (iec 61937) , oba samples and dst packets for oba and sacd with dsd and dst audio streams. the tda19977a; TDA19977B includes a two channel status decoder supporting multi-channel reception for audio sample packets. this enables the user to obtain channel status information from the iec 6 0958/iec 61937 stream such as: ? the audio stream type (non-linear as iec 61937 or l-pcm as iec 60958) ? copyright protection ? sampling frequency refer to iec 60958/iec 61937 specifications for more details. an update of each info frame or the channel status content is indicated by a register bit and the high-to-low transi tion on output pin vai . this makes cpu polling unnecessary. 8.11 audio pll the tda19977a; TDA19977B generates a 128/256/512 f s system clock enabling the use of simple audio dacs without an integrated pll, such as the uda1334bts. the programming of the audio pll can be either automatic, using the audio clock regeneration parameters fo und in the data islands or set manually using the i 2 c-bus. all standard audio sampling frequencies 32 khz, 44.1 khz, 88.2 khz, 176.4 khz, 48 khz, 96 khz and 192 khz are accepted by the device. 8.12 audio formatter audio samples can be output in either s/pdif, i 2 s-bus formats or dsd (sacd). in i 2 s-bus or s/pdif modes, up to eight audio channels can be controlled using the audio port pins (ap0 to ap5). in dsd mode (sacd), up to six audio channels can be controlled using these pins. the audio port mapping depends on the channel allocation (see table 4 , ta b l e 5 and ta b l e 6 for detailed information). www.datasheet.in
tda19977a_TDA19977B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserv ed. product data sheet rev. 3 ? 19 november 2010 13 of 40 nxp semiconductors tda19977a; TDA19977B triple input hdmi receiver interface with digital processing [1] can be activated with the i 2 c-bus (optional). [1] can be activated with the i 2 c-bus (optional). [1] can be activated with the i 2 c-bus (optional). table 4. audio port configuration (layout 0) all audio ports are lv-ttl compatible. audio port pin layout 0 i 2 s-bus s/pdif oba ap5 85 sysclk [1] sysclk [1] ap4 83 ws (word select) ws [1] ap3 82 ap2 81 ap1 80 dsd channel 1 ap0 79 sd s/pdif dsd channel 0 aclk 78 sck (i 2 s-bus clock) 64 f s 32 f s master clock for s/pdif [1] 64 f s dsd clock 64 f s table 5. audio port configuration (layout 1) all audio ports are lv-ttl compatible. audio port pin layout 0 i 2 s-bus s/pdif oba ap5 85 sysclk [1] sysclk [1] dsd channel 5 ap4 83 ws (word select) ws [1] dsd channel 4 ap3 82 sd3 s/pdif3 dsd channel 3 ap2 81 sd2 s/pdif2 dsd channel 2 ap1 80 sd1 s/pdif1 dsd channel 1 ap0 79 sd0 s/pdif0 dsd channel 0 aclk 78 sck (i 2 s-bus clock) 64 f s 32 f s master clock for s/pdif [1] 64 f s dsd clock 64 f s table 6. audio port configur ation for hbr and dst packets all audio ports are lv-ttl compatible. audio port pin hbr demultiplexed dst i 2 s-bus s/pdif ap5 85 sysclk [1] sysclk [1] ap4 83 ws (word select) ws [1] frame_start ap3 82 sdx + 3 s/pdifx + 3 ap2 81 sdx + 2 s/pdifx + 2 ap1 80 sdx + 1 s/pdifx + 1 ap0 79 sdx s/pdifx dsd channel 0 aclk 78 sck (i 2 s-bus clock) 64 f s (acr) 32 f s (acr) master clock for s/pdif [1] 64 f s dsd clock 64 f s 128 f s www.datasheet.in
tda19977a_TDA19977B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserv ed. product data sheet rev. 3 ? 19 november 2010 14 of 40 nxp semiconductors tda19977a; TDA19977B triple input hdmi receiver interface with digital processing 8.13 sync timing measurement to assist input format recognition, the vertic al/horizontal periods and the horizontal pulse width are measured based on the externally generated mclk frequency (27 mhz crystal). this function has an accuracy of 1 lsb = 1 mclk period. 8.14 format measurement timing the tda19977a; TDA19977B includes an impr oved system for accurate recognition of pc and tv formats. this system measures the parameters of blanking and video active area. this function can be useful for example w hen the tda19977a; TDA19977B receives pc format data in hdmi or dvi modes. 8.15 color space conversion the color space conversion enables an rgb si gnal from the hdmi input to be converted into a ycbcr signal or converting the yc bcr signal from the hdmi input into an rgb signal. the color space conversion formula is: (1) activation of the color space conversion func tion, programming of all coefficients and offsets is done using the i 2 c-bus. 8.16 4:2:2 downsampling filters these filters downsample the cb and cr signal s by a factor of 2. a delay has been added to the g/y channel corresponding to the down sample filters pipeline delay to make sure the y channel is in phase with the cb and cr channels. four different filters, from simple cut to it u-r bt.601 compliant digital, can be selected using the i 2 c-bus. 8.17 range control the range control function truncates the range of data to remove super-white and super-black pixels at specif ied ceiling and floor values. 8.18 dithering function the error dispersal rounding (dithering) function can convert the color depth from 30-bit or 36-bit to reduced 30-bit or 24-bit color depth. when dithering is triggered, the tda19977a; TDA19977B applies round, truncate or noise-shaping algorithms. when the error dispersal rounding function is not used, the data coming from the filter is directly sent to the 4:2:2 formatter. the erro r dispersal rounding function works only with the active video signal. yg vr ub c 11 c 12 c 13 c 21 c 22 c 23 c 31 c 32 c 33 cy rv bu o11 o12 o13 + ?? ?? ?? ?? ?? oo1 oo2 oo3 + = www.datasheet.in
tda19977a_TDA19977B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserv ed. product data sheet rev. 3 ? 19 november 2010 15 of 40 nxp semiconductors tda19977a; TDA19977B triple input hdmi receiver interface with digital processing 8.19 4:2:2 formatter the 4:2:2 formatter contains the ycbcr 4:2:2 semi-planar and the ycbcr 4:2:2 itu-r bt.656 formatting functions. the select ion of these functions is made using the i 2 c-bus. ? in ycbcr 4:2:2 mode: the data frequency for the y signal is equal to the pixel clock frequency. while the data frequency for the cb and cr signals is equal to half the pixel clock frequency ? in semi-planar mode: the ou tput clock should be the same as the pixel clock ? in itu-r bt.656 mode: the data frequency should be the same as the formatter clock frequency (e.g. pixel clock 2) the start active video (sav) and end active video (eav) timing reference codes can be included in the data stream based on the href, vref and fref positions from the vhref timing generator. specific codes programmed using the i 2 c-bus can replace the data stream during the blanking period to mask gain and clamp calibration. 8.20 video port selection each channel can be allocated to a specified video port using the i 2 c-bus (see section 13 ? output video port formats ? on page 21 ) to optimize board layout at the interface with video processing ics. for example: ? r, g or b in rgb 4:4:4 mode on vp[29:20] ? y, cb or cr in yuv 4:4:4 mode on vp[19:10] ? y or cb-cr in 4:2:2 semi-planar mode on vp[9:0] ? cb-y-cr-y in 4:2:2 itu-r bt.656 mode on vp[9:0] each video port can be set to high-impedance using the i 2 c-bus. 8.21 output buffers the levels of the output buffers are lv-ttl compatible. switching the outputs between active and high-impedance is set using the i 2 c-bus. the outputs href, vref and fref can be set to high-impedance (z) or forced low (l), independently of the timing reference codes. 8.22 vhref timi ng generator the vhref timing generator outputs all of the timing signals used by the device: ? vref, href and fref signals for sav, eav and active video area definition ? vs and hs to change width and position compared with the hdmi inputs 8.23 i 2 c-bus serial interface the i 2 c-bus serial interface enables the internal registers of the device to be programmed. the slave address of t he device is selected by pin a0. www.datasheet.in
tda19977a_TDA19977B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserv ed. product data sheet rev. 3 ? 19 november 2010 16 of 40 nxp semiconductors tda19977a; TDA19977B triple input hdmi receiver interface with digital processing 8.24 power management the tda19977a; TDA19977B can use one of three power-down modes: ? level 0: full po wer-down mode ? level 1: internal edid memory with i 2 c-bus serial interface active ? level 2: internal edid memory with i 2 c-bus serial interface and activity detection enabled the user can activate these differ ent modes with pin pd or using i 2 c-bus registers: ? level 0: pd pin is high ? level 1: settings defined in the i 2 c-bus registers ? level 2: with settings defined in the i 2 c-bus registers 8.25 edid memory management the tda19977a; TDA19977B embedded edid memory can be shared with all hdmi inputs. the embedded edid memory shares 253 bytes with the three hdmi inputs. in addition, three bytes are dedicated to the physical address and checksum for each hdmi input (see figure 3 ). this memory is accessible in parallel by all hdmi inputs. you can share the edid memory over zero, one, two or three hdmi input(s) as shown in figure 4 . the content of embedded volatile edid memory must be programmed using the i 2 c-bus for each power-on of tda19977a; TDA19977B. the embedded edid memory remains accessible on each hdmi input when the tda19977a; TDA19977B uses a different low-power mode. the ?physical address? of each hdmi inpu t can be easily changed with the tda19977a; TDA19977B without corrupting th e integrity of each ddc-bus. 8.25.1 edid memory shared over all three hdmi inputs (1) 253 bytes + 3 bytes input a + 3 bytes input b + 3 bytes input c + 1 byte address pointer (subphys@): this indica tes the address in each block where the data for inputs a, b and c will be copied. fig 3. an example of an application with edid memory shared over all three hdmi inputs 001aai38 3 edid: 253 b 3 b hdmi input i 2 c-bus cpu flash (1) edid content tda19977 3 b hdmi input 3 b hdmi input www.datasheet.in
tda19977a_TDA19977B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserv ed. product data sheet rev. 3 ? 19 november 2010 17 of 40 nxp semiconductors tda19977a; TDA19977B triple input hdmi receiver interface with digital processing 8.25.2 edid memory shared over two hdmi inputs 9. i 2 c-bus protocol the tda19977a; TDA19977B is a slave i 2 c-bus device and the scl pin is only an input pin. the timing and protocol for i 2 c-bus are standard. bit a0 of the i 2 c-bus device address is externally sele cted by the a0 pin. the main device i 2 c-bus address is given in ta b l e 7 . 10. limiting values (1) 253 bytes + 3 bytes input b + 3 bytes input c + 1 byte address pointer (subphys@): this indica tes the address in each block where the data for inputs b and c will be copied. fig 4. an example of an application with edid memory shared over two hdmi inputs 001aai38 4 edid: 253 b external edid: 256 b or 512 b dvi or hdmi input i 2 c-bus cpu flash (1) edid content tda19977 3 b hdmi input 3 b hdmi input table 7. i 2 c-bus slave address a6 a5 a4 a3 a2 a1 a0 r/w 10011 0a00/1 table 8. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v ddx(3v3) supply voltage on all 3.3 v pins ? 0.5 +4.6 v v ddx(1v8) supply voltage on all 1.8 v pins ? 0.5 +2.5 v v dd supply voltage difference ? 0.5 +0.5 v i o output current - 35 ma t stg storage temperature ? 55 +150 c t amb ambient temperature 0 70 c t j junction temperature - 125 c v esd electrostatic discharge voltage hbm ? 2000 +2000 v www.datasheet.in
tda19977a_TDA19977B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserv ed. product data sheet rev. 3 ? 19 november 2010 18 of 40 nxp semiconductors tda19977a; TDA19977B triple input hdmi receiver interface with digital processing 11. thermal characteristics 12. characteristics table 9. thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient in free air 22.8 k/w r th(j-c) thermal resistance from junction to case 11.1 k/w table 10. characteristics t amb =0 cto70 c; typical values measured at t amb =25 c; unless otherwise specified. symbol parameter conditions min typ max unit supplies v ddh(3v3) hdmi supply voltage (3.3 v) 3.135 3.3 3.465 v v ddh(1v8) hdmi supply voltage (1.8 v) 1.71 1.8 1.89 v v ddi(3v3) input supply voltage (3.3 v) 3.135 3.3 3.465 v v ddc(1v8) core supply voltage (1.8 v) 1.71 1.8 1.89 v v ddo(3v3) output supply voltage (3.3 v) 3.135 3.3 3.465 v i ddh(3v3) hdmi supply current (3.3 v) 720p at 60 hz [1] - 103 - ma 1080p at 60 hz [1] - 106 - ma 1080p at 60 hz; deep color mode [1] -110 - ma i ddh(1v8) hdmi supply current (1.8 v) 720p at 60 hz [1] -48 - ma 1080p at 60 hz [1] -68 - ma 1080p at 60 hz; deep color mode [1] -85 - ma i ddi(3v3) input supply current (3.3 v) 720p at 60 hz [1] -1 - ma 1080p at 60 hz [1] -1 - ma 1080p at 60 hz; deep color mode [1] -1 - ma i ddo(3v3) output supply current (3.3 v) 720p at 60 hz [1] -49 - ma 1080p at 60 hz [1] -78 - ma 1080p at 60 hz; deep color mode [1] - 120 - ma i ddc(1v8) core supply current (1.8 v) 720p at 60 hz [1] - 148 - ma 1080p at 60 hz [1] - 283 - ma 1080p at 60 hz; deep color mode [1] - 453 - ma v dd(3v3-3v3) supply voltage difference between two 3.3 v supplies start-up and established conditions ? 100 - +100 mv v dd(1v8-1v8) supply voltage difference between two 1.8 v supplies start-up and established conditions ? 100 - +100 mv p power dissipation active mode [1] 720p at 60 hz - 0.75 - w 1080p at 60 hz - 1.13 - w 1080p at 60 hz; deep color mode -1.63- w www.datasheet.in
tda19977a_TDA19977B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserv ed. product data sheet rev. 3 ? 19 november 2010 19 of 40 nxp semiconductors tda19977a; TDA19977B triple input hdmi receiver interface with digital processing p cons power consumption power-down mode pin pd = high - 1 - mw i 2 c-bus; edid and hdcp [2] memory power-up -4 - mw i 2 c-bus; edid; activity detection and hdcp [2] memory power-up - 150 - mw clock timing output: pins vclk, aclk and sysclk f clk(max) maximum clock frequency pin vclk 165 - - mhz pin aclk 25 - - mhz pin sysclk 50 - - mhz clk clock duty cycle pin vclk - 50 - % pin aclk - 50 - % pin sysclk - 50 - % timing output: pins vp[29:0]; f s = 165 mhz; c l = 10 pf; see figure 5 t su(q) data output set-up time clkout_del = 0; clkout_tog = 0 1.50 - - ns clkout_del = 1; clkout_tog = 1; clkout_del_sel[2:0] = 4 0.40 - - ns t h(q) data output hold time clkout_del = 0; clkout_tog = 0 0.80 - - ns clkout_del = 1; clkout_tog = 1; clkout_del_sel[2:0] = 4 2.00 - - ns t d(pipe) pipeline delay time from inputs to outputs; all modes; clock interval -80 t clk - timing output: pins ap[5:0 ] with respect to aclk; f clk = 12.288 mhz; c l = 10 pf; see figure 6 t su(q) data output set-up time 69 - - ns t h(q) data output hold time 2 - - ns lv-ttl digital outputs: pins vp[29:0], vclk, ap[5:0], aclk, de, hs, vs, href, vref, fref; c l =10pf v ol low-level output voltage i ol =2ma - - 0.4 v v oh high-level output voltage i oh = ? 2ma 2.4 - - v i loz off-state output leakage current high-impedance state; v o =0v [3] -0 - a v o = v ddo(3v3) 1 3 10 - 100 a v o = v ddo(3v3) 2 3 ? 100 - ? 10 a v o = v ddo(3v3) -0 - a digital inputs: pins rxxc+, rxxc ? [4] v i(dif) differential input voltage r rrx1 =12k 1%; r rrx2 =12k ? 1% 150 - 1200 mv v i(cm) common-mode input voltage 2.735 - 3.475 v f clk(max) maximum clock frequency 205 - - mhz table 10. characteristics ?continued t amb =0 cto70 c; typical values measured at t amb =25 c; unless otherwise specified. symbol parameter conditions min typ max unit www.datasheet.in
tda19977a_TDA19977B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserv ed. product data sheet rev. 3 ? 19 november 2010 20 of 40 nxp semiconductors tda19977a; TDA19977B triple input hdmi receiver interface with digital processing [1] at 30 % activity on video port output. [2] hdcp decoding is only supported by tda19977a. [3] in high-impedance state, the output buffer is set to repeater m ode recopying the input logic state with a small current. the output current changes from most negative to the most positive value at the triggering level which is internally set to v ddo(3v3) / 2 (e.g. the value of a pull-up or pull-down resistor must be lower than 18 k to have a stable output value of v ddo(3v3) or 0 v). [4] x = a, b or c. [5] fast-mode, 5 v tolerant. [6] 5 v tolerant. digital inputs: pins rxx0+, rxx0 ? , rxx1+, rxx1 ? , rxx2+, rxx2 ? [4] v i(dif) differential input voltage r rrx1 =12k ? 1%; r rrx2 =12k ? 1% 150 - 1200 mv v i(cm) common-mode input voltage 2.735 - 3.475 v i 2 c-bus: pins scl and sda [5] f scl scl clock frequency - - 400 khz c b capacitive load for each bus line - - 400 pf c i capacitance for each i/o pin - - 10 pf ddc i 2 c-bus: pins hsclx, hsdax [4] [6] f scl scl clock frequency standard-mode - - 100 khz fast-mode - - 400 khz c i capacitance for each i/o pin - - 10 pf table 10. characteristics ?continued t amb =0 cto70 c; typical values measured at t amb =25 c; unless otherwise specified. symbol parameter conditions min typ max unit fig 5. output timing diagram pin vclk on pins vp[29:0] fig 6. output timing diagram pin aclk on pins ap[5:0] 001aah36 8 vclk 50 % 2.4 v 0.4 v vp[29:0] t su(q) t h(q) 001aah36 9 aclk 50 % 2.4 v 0.4 v ap[5:0] t su(q) t h(q) www.datasheet.in
tda19977a_TDA19977B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserv ed. product data sheet rev. 3 ? 19 november 2010 21 of 40 nxp semiconductors tda19977a; TDA19977B triple input hdmi receiver interface with digital processing 13. output video port formats [1] z = high-impedance; l = low-level; depending on bit vpl. table 11. output in 12-bit video port format (register vp_ctrl address = 21h) signal ycbcr 4:2:2 semi-planar [1] ycbcr 4:2:2 itu-r bt.656 [1] vp[29] y 0 [11] y 1 [11] z/l z/l z/l z/l vp[28] y 0 [10] y 1 [10] z/l z/l z/l z/l vp[27] y 0 [9] y 1 [9] z/l z/l z/l z/l vp[26] y 0 [8] y 1 [8] z/l z/l z/l z/l vp[25] y 0 [7] y 1 [7] z/l z/l z/l z/l vp[24] y 0 [6] y 1 [6] z/l z/l z/l z/l vp[23] y 0 [5] y 1 [5] z/l z/l z/l z/l vp[22] y 0 [4] y 1 [4] z/l z/l z/l z/l vp[21] y 0 [3] y 1 [3] z/l z/l z/l z/l vp[20] y 0 [2] y 1 [2] z/l z/l z/l z/l vp[19] y 0 [1] y 1 [1] z/l z/l z/l z/l vp[18] y 0 [0] y 1 [0] z/l z/l z/l z/l vp[17] cb[11] cr[11] cb[11] y 0 [11] cr[11] y 1 [11] vp[16] cb[10] cr[10] cb[10] y 0 [10] cr[10] y 1 [10] vp[15] cb[9] cr[9] cb[9] y 0 [9] cr[9] y 1 [9] vp[14] cb[8] cr[8] cb[8] y 0 [8] cr[8] y 1 [8] vp[13] cb[7] cr[7] cb[7] y 0 [7] cr[7] y 1 [7] vp[12] cb[6] cr[6] cb[6] y 0 [6] cr[6] y 1 [6] vp[11] cb[5] cr[5] cb[5] y 0 [5] cr[5] y 1 [5] vp[10] cb[4] cr[4] cb[4] y 0 [4] cr[4] y 1 [4] vp[9] cb[3] cr[3] cb[3] y 0 [3] cr[3] y 1 [3] vp[8] cb[2] cr[2] cb[2] y 0 [2] cr[2] y 1 [2] vp[7] cb[1] cr[1] cb[1] y 0 [1] cr[1] y 1 [1] vp[6] cb[0] cr[0] cb[0] y 0 [0] cr[0] y 1 [0] vp[5]z/lz/lz/lz/lz/lz/l vp[4]z/lz/lz/lz/lz/lz/l vp[3]z/lz/lz/lz/lz/lz/l vp[2]z/lz/lz/lz/lz/lz/l vp[1]z/lz/lz/lz/lz/lz/l vp[0]z/lz/lz/lz/lz/lz/l www.datasheet.in
tda19977a_TDA19977B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserv ed. product data sheet rev. 3 ? 19 november 2010 22 of 40 nxp semiconductors tda19977a; TDA19977B triple input hdmi receiver interface with digital processing [1] z = high-impedance; l = low-level; depending on bit vpl. table 12. output in 12-bit video port format (register vp_ctrl address = 09h) signal ycbcr 4:2:2 semi-planar [1] ycbcr 4:2:2 itu-r bt.656 [1] vp[29] cb[11] cr[11] cb[11] y 0 [11] cr[11] y 1 [11] vp[28] cb[10] cr[10] cb[10] y 0 [10] cr[10] y 1 [10] vp[27] cb[9] cr[9] cb[9] y 0 [9] cr[9] y 1 [9] vp[26] cb[8] cr[8] cb[8] y 0 [8] cr[8] y 1 [8] vp[25] cb[7] cr[7] cb[7] y 0 [7] cr[7] y 1 [7] vp[24] cb[6] cr[6] cb[6] y 0 [6] cr[6] y 1 [6] vp[23] cb[5] cr[5] cb[5] y 0 [5] cr[5] y 1 [5] vp[22] cb[4] cr[4] cb[4] y 0 [4] cr[4] y 1 [4] vp[21] cb[3] cr[3] cb[3] y 0 [3] cr[3] y 1 [3] vp[20] cb[2] cr[2] cb[2] y 0 [2] cr[2] y 1 [2] vp[19] cb[1] cr[1] cb[1] y 0 [1] cr[1] y 1 [1] vp[18] cb[0] cr[0] cb[0] y 0 [0] cr[0] y 1 [0] vp[17] y 0 [11] y 1 [11] z/l z/l z/l z/l vp[16] y 0 [10] y 1 [10] z/l z/l z/l z/l vp[15] y 0 [9] y 1 [9] z/l z/l z/l z/l vp[14] y 0 [8] y 1 [8] z/l z/l z/l z/l vp[13] y 0 [7] y 1 [7] z/l z/l z/l z/l vp[12] y 0 [6] y 1 [6] z/l z/l z/l z/l vp[11] y 0 [5] y 1 [5] z/l z/l z/l z/l vp[10] y 0 [4] y 1 [4] z/l z/l z/l z/l vp[9] y 0 [3] y 1 [3] z/l z/l z/l z/l vp[8] y 0 [2] y 1 [2] z/l z/l z/l z/l vp[7] y 0 [1] y 1 [1] z/l z/l z/l z/l vp[6] y 0 [0] y 1 [0] z/l z/l z/l z/l vp[5] z/l z/l z/l z/l z/l z/l vp[4] z/l z/l z/l z/l z/l z/l vp[3] z/l z/l z/l z/l z/l z/l vp[2] z/l z/l z/l z/l z/l z/l vp[1] z/l z/l z/l z/l z/l z/l vp[0] z/l z/l z/l z/l z/l z/l www.datasheet.in
tda19977a_TDA19977B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserv ed. product data sheet rev. 3 ? 19 november 2010 23 of 40 nxp semiconductors tda19977a; TDA19977B triple input hdmi receiver interface with digital processing [1] z = high-impedance; l = low-level; depending on bit vpl. table 13. output in 10-bit video port format (register vp_ctrl address = 61h) signal rgb ycbcr 4:4:4 ycbcr 4:2:2 semi-planar [1] ycbcr 4:2:2 itu-r bt.656 [1] vp[29] g[11] y[11] y 0 [11] y 1 [11] z/l z/l z/l z/l vp[28] g[10] y[10] y 0 [10] y 1 [10] z/l z/l z/l z/l vp[27] g[9] y[9] y 0 [9] y 1 [9] z/l z/l z/l z/l vp[26] g[8] y[8] y 0 [8] y 1 [8] z/l z/l z/l z/l vp[25] g[7] y[7] y 0 [7] y 1 [7] z/l z/l z/l z/l vp[24] g[6] y[6] y 0 [6] y 1 [6] z/l z/l z/l z/l vp[23] g[5] y[5] y 0 [5] y 1 [5] z/l z/l z/l z/l vp[22] g[4] y[4] y 0 [4] y 1 [4] z/l z/l z/l z/l vp[21] g[3] y[3] y 0 [3] y 1 [3] z/l z/l z/l z/l vp[20] g[2] y[2] y 0 [2] y 1 [2] z/l z/l z/l z/l vp[19] r[11] cr[11] cb[11] cr[11] cb[11] y 0 [11] cr[11] y 1 [11] vp[18] r[10] cr[10] cb[10] cr[10] cb[10] y 0 [10] cr[10] y 1 [10] vp[17] r[9] cr[9] cb[9] cr[9] cb[9] y 0 [9] cr[9] y 1 [9] vp[16] r[8] cr[8] cb[8] cr[8] cb[8] y 0 [8] cr[8] y 1 [8] vp[15] r[7] cr[7] cb[7] cr[7] cb[7] y 0 [7] cr[7] y 1 [7] vp[14] r[6] cr[6] cb[6] cr[6] cb[6] y 0 [6] cr[6] y 1 [6] vp[13] r[5] cr[5] cb[5] cr[5] cb[5] y 0 [5] cr[5] y 1 [5] vp[12] r[4] cr[4] cb[4] cr[4] cb[4] y 0 [4] cr[4] y 1 [4] vp[11] r[3] cr[3] cb[3] cr[3] cb[3] y 0 [3] cr[3] y 1 [3] vp[10] r[2] cr[2] cb[2] cr[2] cb[2] y 0 [2] cr[2] y 1 [2] vp[9] b[11] cb[11] z/l z/l z/l z/l z/l z/l vp[8] b[10] cb[10] z/l z/l z/l z/l z/l z/l vp[7] b[9] cb[9] z/l z/l z/l z/l z/l z/l vp[6] b[8] cb[8] z/l z/l z/l z/l z/l z/l vp[5] b[7] cb[7] z/l z/l z/l z/l z/l z/l vp[4] b[6] cb[6] z/l z/l z/l z/l z/l z/l vp[3] b[5] cb[5] z/l z/l z/l z/l z/l z/l vp[2] b[4] cb[4] z/l z/l z/l z/l z/l z/l vp[1] b[3] cb[3] z/l z/l z/l z/l z/l z/l vp[0] b[2] cb[2] z/l z/l z/l z/l z/l z/l www.datasheet.in
tda19977a_TDA19977B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserv ed. product data sheet rev. 3 ? 19 november 2010 24 of 40 nxp semiconductors tda19977a; TDA19977B triple input hdmi receiver interface with digital processing [1] z = high-impedance; l = low-level; depending on bit vpl. table 14. output in 10-bit video port format (register vp_ctrl address = 58h) signal rgb ycbcr 4:4:4 ycbcr 4:2:2 semi-planar [1] ycbcr 4:2:2 itu-r bt.656 [1] vp[29] b[11] cb[11] z/l z/l z/l z/l z/l z/l vp[28] b[10] cb[10] z/l z/l z/l z/l z/l z/l vp[27] b[9] cb[9] z/l z/l z/l z/l z/l z/l vp[26] b[8] cb[8] z/l z/l z/l z/l z/l z/l vp[25] b[7] cb[7] z/l z/l z/l z/l z/l z/l vp[24] b[6] cb[6] z/l z/l z/l z/l z/l z/l vp[23] b[5] cb[5] z/l z/l z/l z/l z/l z/l vp[22] b[4] cb[4] z/l z/l z/l z/l z/l z/l vp[21] b[3] cb[3] z/l z/l z/l z/l z/l z/l vp[20] b[2] cb[2] z/l z/l z/l z/l z/l z/l vp[19] g[11] y[11] y 0 [11] y 1 [11] z/l z/l z/l z/l vp[18] g[10] y[10] y 0 [10] y 1 [10] z/l z/l z/l z/l vp[17] g[9] y[9] y 0 [9] y 1 [9] z/l z/l z/l z/l vp[16] g[8] y[8] y 0 [8] y 1 [8] z/l z/l z/l z/l vp[15] g[7] y[7] y 0 [7] y 1 [7] z/l z/l z/l z/l vp[14] g[6] y[6] y 0 [6] y 1 [6] z/l z/l z/l z/l vp[13] g[5] y[5] y 0 [5] y 1 [5] z/l z/l z/l z/l vp[12] g[4] y[4] y 0 [4] y 1 [4] z/l z/l z/l z/l vp[11] g[3] y[3] y 0 [3] y 1 [3] z/l z/l z/l z/l vp[10] g[2] y[2] y 0 [2] y 1 [2] z/l z/l z/l z/l vp[9] r[11] cr[11] cb[11] cr[11] cb[11] y 0 [11] cr[11] y 1 [11] vp[8] r[10] cr[10] cb[10] cr[10] cb[10] y 0 [10] cr[10] y 1 [10] vp[7] r[9] cr[9] cb[9] cr[9] cb[9] y 0 [9] cr[9] y 1 [9] vp[6] r[8] cr[8] cb[8] cr[8] cb[8] y 0 [8] cr[8] y 1 [8] vp[5] r[7] cr[7] cb[7] cr[7] cb[7] y 0 [7] cr[7] y 1 [7] vp[4] r[6] cr[6] cb[6] cr[6] cb[6] y 0 [6] cr[6] y 1 [6] vp[3] r[5] cr[5] cb[5] cr[5] cb[5] y 0 [5] cr[5] y 1 [5] vp[2] r[4] cr[4] cb[4] cr[4] cb[4] y 0 [4] cr[4] y 1 [4] vp[1] r[3] cr[3] cb[3] cr[3] cb[3] y 0 [3] cr[3] y 1 [3] vp[0] r[2] cr[2] cb[2] cr[2] cb[2] y 0 [2] cr[2] y 1 [2] www.datasheet.in
tda19977a_TDA19977B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserv ed. product data sheet rev. 3 ? 19 november 2010 25 of 40 nxp semiconductors tda19977a; TDA19977B triple input hdmi receiver interface with digital processing [1] z = high-impedance; l = low-level; depending on bit vpl. table 15. output in 8-bit video port format (register vp_ct rl address = a1h) signal rgb [1] ycbcr 4:4:4 [1] ycbcr 4:2:2 semi-planar [1] ycbcr 4:2:2 itu-r bt.656 [1] vp[29] g[11] y[11] y 0 [11] y 1 [11] z/l z/l z/l z/l vp[28] g[10] y[10] y 0 [10] y 1 [10] z/l z/l z/l z/l vp[27] g[9] y[9] y 0 [9] y 1 [9] z/l z/l z/l z/l vp[26] g[8] y[8] y 0 [8] y 1 [8] z/l z/l z/l z/l vp[25] g[7] y[7] y 0 [7] y 1 [7] z/l z/l z/l z/l vp[24] g[6] y[6] y 0 [6] y 1 [6] z/l z/l z/l z/l vp[23] g[5] y[5] y 0 [5] y 1 [5] z/l z/l z/l z/l vp[22] g[4] y[4] y 0 [4] y 1 [4] z/l z/l z/l z/l vp[21] r[11] cr[11] cb[11] cr[11] cb[11] y 0 [11] cr[11] y 1 [11] vp[20] r[10] cr[10] cb[10] cr[10] cb[10] y 0 [10] cr[10] y 1 [10] vp[19] r[9] cr[9] cb[9] cr[9] cb[9] y 0 [9] cr[9] y 1 [9] vp[18] r[8] cr[8] cb[8] cr[8] cb[8] y 0 [8] cr[8] y 1 [8] vp[17] r[7] cr[7] cb[7] cr[7] cb[7] y 0 [7] cr[7] y 1 [7] vp[16] r[6] cr[6] cb[6] cr[6] cb[6] y 0 [6] cr[6] y 1 [6] vp[15] r[5] cr[5] cb[5] cr[5] cb[5] y 0 [5] cr[5] y 1 [5] vp[14] r[4] cr[4] cb[4] cr[4] cb[4] y 0 [4] cr[4] y 1 [4] vp[13] b[11] cb[11] z/l z/l z/l z/l z/l z/l vp[12] b[10] cb[10] z/l z/l z/l z/l z/l z/l vp[11] b[9] cb[9] z/l z/l z/l z/l z/l z/l vp[10] b[8] cb[8] z/l z/l z/l z/l z/l z/l vp[9] b[7] cb[7] z/l z/l z/l z/l z/l z/l vp[8] b[6] cb[6] z/l z/l z/l z/l z/l z/l vp[7] b[5] cb[5] z/l z/l z/l z/l z/l z/l vp[6] b[4] cb[4] z/l z/l z/l z/l z/l z/l vp[5] z/l z/l z/l z/l z/l z/l z/l z/l vp[4] z/l z/l z/l z/l z/l z/l z/l z/l vp[3] z/l z/l z/l z/l z/l z/l z/l z/l vp[2] z/l z/l z/l z/l z/l z/l z/l z/l vp[1] z/l z/l z/l z/l z/l z/l z/l z/l vp[0] z/l z/l z/l z/l z/l z/l z/l z/l www.datasheet.in
tda19977a_TDA19977B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserv ed. product data sheet rev. 3 ? 19 november 2010 26 of 40 nxp semiconductors tda19977a; TDA19977B triple input hdmi receiver interface with digital processing [1] z = high-impedance; l = low-level; depending on bit vpl. table 16. output in 8-bit video port format (register vp_ctrl address = 98h) signal rgb [1] ycbcr 4:4:4 [1] ycbcr 4:2:2 semi-planar [1] ycbcr 4:2:2 itu-r bt.656 [1] vp[29] b[11] cb[11] z/l z/l z/l z/l z/l z/l vp[28] b[10] cb[10] z/l z/l z/l z/l z/l z/l vp[27] b[9] cb[9] z/l z/l z/l z/l z/l z/l vp[26] b[8] cb[8] z/l z/l z/l z/l z/l z/l vp[25] b[7] cb[7] z/l z/l z/l z/l z/l z/l vp[24] b[6] cb[6] z/l z/l z/l z/l z/l z/l vp[23] b[5] cb[5] z/l z/l z/l z/l z/l z/l vp[22] b[4] cb[4] z/l z/l z/l z/l z/l z/l vp[21] g[11] y[11] y 0 [11] y 1 [11] z/l z/l z/l z/l vp[20] g[10] y[10] y 0 [10] y 1 [10] z/l z/l z/l z/l vp[19] g[9] y[9] y 0 [9] y 1 [9] z/l z/l z/l z/l vp[18] g[8] y[8] y 0 [8] y 1 [8] z/l z/l z/l z/l vp[17] g[7] y[7] y 0 [7] y 1 [7] z/l z/l z/l z/l vp[16] g[6] y[6] y 0 [6] y 1 [6] z/l z/l z/l z/l vp[15] g[5] y[5] y 0 [5] y 1 [5] z/l z/l z/l z/l vp[14] g[4] y[4] y 0 [4] y 1 [4] z/l z/l z/l z/l vp[13] r[11] cr[11] cb[11] cr[11] cb[11] y 0 [11] cr[11] y 1 [11] vp[12] r[10] cr[10] cb[10] cr[10] cb[10] y 0 [10] cr[10] y 1 [10] vp[11] r[9] cr[9] cb[9] cr[9] cb[9] y 0 [9] cr[9] y 1 [9] vp[10] r[8] cr[8] cb[8] cr[8] cb[8] y 0 [8] cr[8] y 1 [8] vp[9] r[7] cr[7] cb[7] cr[7] cb[7] y 0 [7] cr[7] y 1 [7] vp[8] r[6] cr[6] cb[6] cr[6] cb[6] y 0 [6] cr[6] y 1 [6] vp[7] r[5] cr[5] cb[5] cr[5] cb[5] y 0 [5] cr[5] y 1 [5] vp[6] r[4] cr[4] cb[4] cr[4] cb[4] y 0 [4] cr[4] y 1 [4] vp[5] z/l z/l z/l z/l z/l z/l z/l z/l vp[4] z/l z/l z/l z/l z/l z/l z/l z/l vp[3] z/l z/l z/l z/l z/l z/l z/l z/l vp[2] z/l z/l z/l z/l z/l z/l z/l z/l vp[1] z/l z/l z/l z/l z/l z/l z/l z/l vp[0] z/l z/l z/l z/l z/l z/l z/l z/l www.datasheet.in
tda19977a_TDA19977B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserv ed. product data sheet rev. 3 ? 19 november 2010 27 of 40 nxp semiconductors tda19977a; TDA19977B triple input hdmi receiver interface with digital processing 14. example of supported video formats table 17. example of supported video formats standard format total pixels total lines horizontal rate (khz) pixel clock rate (mhz) [1] 576i [2] 1440 576i 50 hz 1728 625 15.750 27.000 [3] 480i [4] 1440 480i 59.94 hz 1716 525 15.734 27.000 [3] 1440 480i 60 hz 1716 525 15.750 27.027 [3] 576p 720 576p 50 hz 864 625 31.250 27.000 480p 720 480p 59.94 hz 858 525 31.469 27.000 720 480p 60 hz 858 525 31.500 27.027 720p 1280 720p 50 hz 1980 750 37.500 74.250 1280 720p 59.94 hz 1650 750 44.955 74.176 1280 720p 60 hz 1650 750 45.000 74.250 1080i 1920 1080i 50 hz 2640 1125 28.125 74.250 1920 1080i 59.94 hz 2200 1125 33.716 74.176 1920 1080i 60 hz 2200 1125 33.750 74.250 1080p 1920 1080p 50 hz [5] 2640 1125 56.250 148.500 1920 1080p 59.94 hz [5] 2200 1125 67.433 148.352 1920 1080p 60 hz [5] 2200 1125 67.500 148.500 0.31m3 vga 640 480p 60 hz 800 525 31.469 25.175 640 480p 72 hz 832 520 37.861 31.500 640 480p 75 hz 840 500 37.500 31.500 640 480p 85 hz 832 509 43.269 36.000 0.48m3 svga 800 600p 56 hz 1024 625 35.156 36.000 800 600p 60 hz 1056 628 37.879 40.000 800 600p 72 hz 1040 666 48.077 50.000 800 600p 75 hz 1056 625 46.875 49.500 800 600p 85 hz 1048 631 53.674 56.250 0.48m3-r 800 600p 120 hz 960 636 76.302 73.250 0.41m9 848 480p 60 hz 1088 517 31.020 33.750 0.79m3 xga 1024 768p 43 hz 1264 817 35.522 44.900 1024 768p 60 hz 1344 806 48.363 65.000 1024 768p 70 hz 1328 806 56.476 75.000 1024 768p 75 hz 1312 800 60.023 78.750 1024 768p 85 hz 1376 808 68.677 94.500 0.79m3-r xga 1024 768p 120 hz 1184 813 97.551 115.500 1.00m3 1152 864p 75 hz 1600 900 67.500 108.000 0.98m9-r 1280 768p 60 hz 1440 790 47.396 68.250 1280 768p 120 hz [5] 1440 813 97.396 140.250 0.98m9 1280 768p 60 hz 1664 798 47.776 79.500 1280 768p 75 hz 1696 805 60.289 102.250 1280 768p 85 hz 1712 809 68.633 117.500 www.datasheet.in
tda19977a_TDA19977B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserv ed. product data sheet rev. 3 ? 19 november 2010 28 of 40 nxp semiconductors tda19977a; TDA19977B triple input hdmi receiver interface with digital processing [1] pixel clock rate corresponds to vclk output for 4:4:4 format and 4:2:2 semi-planar; vclk / 2 for 4:2:2 itu-r bt.656 format. the pixel clock rate can be determined by: a) total pixels total lines frame rate for the progressive format. b) total pixels total lines frame rate / 2 for the interlaced format. [2] also referred to as pa l (phase alternating line). [3] pixel-doubling. [4] also referred to as ntsc (nati onal television standards committee). [5] only supports deep color mode 10-bit. [6] sometimes also referred to as wuxg a (wide ultra extended graphics array). 1.02ma-r 1280 800p 60 hz 1440 823 49.306 71.000 1280 800p 120 hz [5] 1440 847 101.563 146.250 1.02ma 1280 800p 60 hz 1680 831 49.702 83.500 1280 800p 75 hz 1696 838 62.795 106.500 1280 800p 85 hz 1712 843 71.554 122.500 1.23m3 1280 960p 60 hz 1800 1000 60.000 108.000 1280 960p 85 hz [5] 1728 1011 85.938 148.500 1.31m4 sxga 1280 1024p 60 hz 1688 1066 63.981 108.000 1280 1024p 75 hz 1688 1066 79.976 135.000 1280 1024p 85 hz [5] 1728 1072 91.146 157.500 1.04m9 1360 768p 60 hz 1792 795 47.712 85.500 1.04m9-r 1360 768p 120 hz [5] 1520 813 97.533 148.250 1.47m3-r 1400 1050p 60 hz 1560 1080 64.744 101.000 1.47m3 1400 1050p 60 hz 1864 1089 65.317 121.750 1400 1050p 75 hz [5] 1896 1099 82.278 156.000 1.29ma-r 1440 900p 60 hz 1600 926 55.469 88.750 1.29ma 1440 900p 60 hz 1904 934 55.935 106.500 1440 900p 75 hz [5] 1936 942 70.635 136.750 1440 900p 85 hz [5] 1952 948 80.430 157.000 1.92m3 uxga 1600 1200p 60 hz [5] 2160 1250 75.000 162.000 1.76ma-r 1680 1050p 60 hz 1840 1080 64.674 119.000 1.76ma 1680 1050p 60 hz [5] 2240 1089 65.290 146.250 2.30ma-r [6] 1920 1200p 60 hz [5] 2080 1235 74.038 154.000 table 18. examples of 3d vide o formats timing supported resolution 3d transmission type 1280 720p at 23.98 hz and 24 hz frame packing, side-by-side (half), top-and-bottom 1280 720p at 25 hz frame packing, side- by-side (half), top-and-bottom 1280 720p at 29.97 hz and 30 hz frame packing, side-by-side (half), top-and-bottom 1280 720p at 50 hz frame packing, si de-by-side (half), top-and-bottom 1280 720p at 59.94 hz and 60 hz frame packi ng, side-by-side (half), top-and-bottom 1920 1080i at 50 hz frame packing [1] , side-by-side (half), top-and-bottom table 17. example of supported video formats ?continued standard format total pixels total lines horizontal rate (khz) pixel clock rate (mhz) [1] www.datasheet.in
tda19977a_TDA19977B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserv ed. product data sheet rev. 3 ? 19 november 2010 29 of 40 nxp semiconductors tda19977a; TDA19977B triple input hdmi receiver interface with digital processing [1] only available without timing code and blanking code. tda19977a; TDA19977B support other 3d vide o formats so software implementation can be considered on request. 1920 1080i at 59.94 hz and 60 hz frame packing [1] , side-by-side (half), top-and-bottom 1920 1080p at 23.98 hz and 24 hz frame packing [1] , side-by-side (half), top-and-bottom 1920 1080p at 25 hz frame packing [1] , side-by-side (half), top-and-bottom 1920 1080p at 29.97 hz and 30 hz frame packing [1] , side-by-side (half), top-and-bottom 1920 1080p at 50 hz side-by-side (half), top-and-bottom 1920 1080p at 59.94 hz and 60 hz side-by-side (half), top-and-bottom table 18. examples of 3d vide o formats timing supported ?continued resolution 3d transmission type www.datasheet.in
tda19977a_TDA19977B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserv ed. product data sheet rev. 3 ? 19 november 2010 30 of 40 nxp semiconductors tda19977a; TDA19977B triple input hdmi receiver interface with digital processing 15. application information fig 7. application diagram of tda19977a; TDA19977B 001aai38 5 0 12 k 1% v ssc 108 1 v ddh(1v8) tda19977 pd 107 2 v ddc(1v8) v ddh(3v3) 3.3 v hdmi 3.3 v hdmi 1.8 v dig 3.3 v dig 1.8 v dig 3.3 v dig 1.8 v dig 3.3 v dig 3.3 v dig 3.3 v dig 3.3 v hdmi 3.3 v hdmi 3.3 v hdmi 3.3 v hdmi 12 k 1% 3.3 v hdmi 1.8 v hdmi 3.3 v hdmi 3.3 v hdmi 3.3 v hdmi 1.8 v hdmi 1.8 v dig 3.3 v dig_i 1.8 v dig 1.8 v hdmi 1.8 v dig 1.8 v hdmi 1.8 v dig 3.3 v dig_i 3.3 v dig 3.3 v hdmi 1.8 v hdmi 106 3 rrx1 n.c. 105 4 v ssh n.c. 104 5 v ddh(3v3) v ssh 103 6 test0 rxcc ? 102 7 hsclb rxcc+ 101 8 hsdab v ddh(3v3) 100 9 hscla n.c. 99 10 hsdaa n.c. 98 11 scl v ssh 97 12 sda rxc0 ? 96 13 vai rxc0+ 95 14 v ddi(3v3) v ddh(1v8) 94 15 xtalin/mclk n.c. 93 16 xtalout n.c. 92 17 v ddc(1v8) v ssh 91 18 v ssh rxc1 ? 90 19 v ddh(1v8) rxc1+ 89 20 v ssh v ddh(3v3) 88 21 v ddh(3v3) n.c. 87 22 v ddh(3v3) n.c. 86 23 v sso v ssh 85 24 ap5/sysclk rxc2 ? 84 25 v ddo(3v3) rxc2+ 83 26 ap4/ws v pp 82 27 ap3 gndc gndc gndc gndc gndc gndc v ddc(1v8) 81 28 ap2 v ddo(3v3) 80 29 ap1 vclk 79 30 ap0 v sso 78 31 aclk cs/fref 77 32 v sso vs/vref 76 33 vp[29] hs/href 75 34 vp[28] de 74 35 v ddo(3v3) vp[0] 73 36 v ssc v ssc 144 37 v ddh(1v8) vp[1] 143 38 rrx2 vp[2] 142 39 v ddi(3v3) vp[3] 141 40 n.c. hdmi inputs c hdmi inputs a and b control outputs and video port outputs ddc c i 2 c-bus 27 mhz ddc a and b audio port output v ddo(3v3) 140 41 n.c. v ddc(1v8) 139 42 hsclc v sso 138 43 hsdac vp[4] 137 44 v ddc(1v8) vp[5] 136 45 v ddc(1v8) vp[6] 135 46 v ssh vp[7] 134 47 rxa2+ vp[8] 133 48 rxa2 ? vp[9] 132 49 v ssh vp[10] 131 50 rxb2 ? vp[11] 130 51 rxb2+ v ddo(3v3) 129 52 v ddh(3v3) vp[12] 128 53 rxa1+ v sso 127 54 rxa1 ? vp[13] 126 55 v ssh vp[14] 125 56 rxb1 ? vp[15] 124 57 rxb1+ vp[16] 123 58 v ddh(1v8) vp[17] 122 59 rxa0+ vp[18] 121 60 rxa0 ? vp[19] 120 61 v ssh vp[20] 119 62 rxb0 ? v ddo(3v3) 118 63 rxb0+ v ddc(1v8) 117 64 v ddh(3v3) v sso 116 65 rxac+ vp[21] 115 66 rxac ? vp[22] 114 67 v ssh vp[23] 113 68 rxbc ? vp[24] 112 69 rxbc+ vp[25] 111 70 v ddh(3v3) vp[26] 110 71 a0 vp[27] 109 72 v ssc www.datasheet.in
tda19977a_TDA19977B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserv ed. product data sheet rev. 3 ? 19 november 2010 31 of 40 nxp semiconductors tda19977a; TDA19977B triple input hdmi receiver interface with digital processing 16. package outline fig 8. package outline sot612-3 (hlqfp144) unit a 1 a 2 a 3 b p ceh e h d ll p z e (1) z d (1) y w v references outline version european projection issue date iec jedec jeita mm 0.12 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 20.1 19.9 0.5 22.15 21.85 1.4 1.1 7 0 o o 0.08 0.2 0.08 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot612-3 ms-026 02-07-12 04-07-05 d (1) e (1) 20.1 19.9 d h 5.7 5.5 e h 5.7 5.5 22.15 21.85 1.4 1.1 0 5 10 mm scale b p e e a 1 a l p detail x l (a ) 3 b c b p e h a 2 d h v m b d z d a z e e v m a x y w m w m a max. 1.6 h lqfp144: plastic thermal enhanced low profile quad flat package; 144 leads; b ody 20 x 20 x 1.4 mm; exposed die pad sot612- 3 108 109 pin 1 index e h d h exposed die pad 73 72 37 1 144 36 www.datasheet.in
tda19977a_TDA19977B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserv ed. product data sheet rev. 3 ? 19 november 2010 32 of 40 nxp semiconductors tda19977a; TDA19977B triple input hdmi receiver interface with digital processing 17. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 17.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 17.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 17.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities www.datasheet.in
tda19977a_TDA19977B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserv ed. product data sheet rev. 3 ? 19 november 2010 33 of 40 nxp semiconductors tda19977a; TDA19977B triple input hdmi receiver interface with digital processing 17.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 9 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and coolin g down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 1 9 and 20 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 9 . table 19. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 < 2.5 235 220 2.5 220 220 table 20. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 www.datasheet.in
tda19977a_TDA19977B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserv ed. product data sheet rev. 3 ? 19 november 2010 34 of 40 nxp semiconductors tda19977a; TDA19977B triple input hdmi receiver interface with digital processing for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . msl: moisture sensitivity level fig 9. temperature profiles for large and small components 001aac84 4 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature www.datasheet.in
tda19977a_TDA19977B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserv ed. product data sheet rev. 3 ? 19 november 2010 35 of 40 nxp semiconductors tda19977a; TDA19977B triple input hdmi receiver interface with digital processing 18. abbreviations table 21. abbreviations acronym description acr audio clock regeneration avr audio video receiver awg american wire gauge cmos complementary metal-oxide-semiconductor dac digital-to-analog converter ddc-bus display data channel bus dsd direct stream digital dst direct stream transfer dts-hd digital theater systems high-definition dvd digital versatile disc dvi digital video interface edid extended display identification data hbm human body model hbr high bit rate hd high-definition hdcp high-bandwidth digital content protection hdmi high-definition multimedia interface hdtv high-definition television l-pcm linear-pulse code modulation lsb least significant bit lv-ttl low voltage transistor-transistor logic oba one bit audio otp one time programmable pll phase-locked loop rgb red green blue sacd super audio cd svga super video graphics array sxga super extended graphics array s/pdif sony/philips digital interface format tmds transition minimized differential signaling uxga ultra extended graphics array vga video graphics array wuxga wide ultra extended graphics array xga extended graphics array ycbcr y = luminance, cb = chroma blue, cr = chroma red www.datasheet.in
tda19977a_TDA19977B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserv ed. product data sheet rev. 3 ? 19 november 2010 36 of 40 nxp semiconductors tda19977a; TDA19977B triple input hdmi receiver interface with digital processing 19. revision history table 22. revision history document id release date data sheet status change notice supersedes tda19977a_TDA19977B v.3 20101119 product data sheet - tda19977a_TDA19977B v.2 modifications: ? replaced in all document hdmi 1.3a with hdmi 1.4a ? replaced in all document hdcp 1.2 with hdcp 1.4 ? ta b l e 1 8 : added tda19977a_TDA19977B v.2 20100511 product data sheet - tda19977a_TDA19977B v.1 tda19977a_TDA19977B v.1 20080807 product data sheet - - www.datasheet.in
tda19977a_TDA19977B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserv ed. product data sheet rev. 3 ? 19 november 2010 37 of 40 nxp semiconductors tda19977a; TDA19977B triple input hdmi receiver interface with digital processing 20. legal information 20.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. 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stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification. www.datasheet.in
tda19977a_TDA19977B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserv ed. product data sheet rev. 3 ? 19 november 2010 38 of 40 nxp semiconductors tda19977a; TDA19977B triple input hdmi receiver interface with digital processing quick reference data ? the quick reference data is an extract of the product data given in the limiting values and characteristics sections of this document, and as such is not comple te, exhaustive or legally binding. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive s pecifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully in demnifies nxp semi conductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive appl ications beyond nxp semiconductors? standard warranty and nxp semicond uctors? product specifications. 20.4 licenses 20.5 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 21. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com purchase of nxp ics with hdmi technology use of an nxp ic with hdmi technology in equipment that complies with the hdmi standard requires a license from hdmi licensing llc, 1060 e. arques avenue suite 100, sunnyvale ca 94085, usa, e-mail: admin@hdmi.org . www.datasheet.in
tda19977a_TDA19977B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserv ed. product data sheet rev. 3 ? 19 november 2010 39 of 40 nxp semiconductors tda19977a; TDA19977B triple input hdmi receiver interface with digital processing 22. tables table 1. quick reference data . . . . . . . . . . . . . . . . . . . . .3 table 2. ordering information . . . . . . . . . . . . . . . . . . . . .4 table 3. pin description . . . . . . . . . . . . . . . . . . . . . . . . . .6 table 4. audio port configuration (layout 0) . . . . . . . . .13 table 5. audio port configuration (layout 1) . . . . . . . . .13 table 6. audio port configuration for hbr and dst packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 7. i 2 c-bus slave address . . . . . . . . . . . . . . . . . . .17 table 8. limiting values . . . . . . . . . . . . . . . . . . . . . . . . .17 table 9. thermal characteristics . . . . . . . . . . . . . . . . . .18 table 10. characteristics . . . . . . . . . . . . . . . . . . . . . . . . .18 table 11. output in 12-bit video port format (register vp_ctrl address = 21h) . . . . . . . . . . . . . . . .21 table 12. output in 12-bit video port format (register vp_ctrl address = 09h) . . . . . . . . . . . . . . . .22 table 13. output in 10-bit video port format (register vp_ctrl address = 61h) . . . . . . . . . . . . . . . . 23 table 14. output in 10-bit video port format (register vp_ctrl address = 58h) . . . . . . . . . . . . . . . . 24 table 15. output in 8-bit video port format (register vp_ctrl address = a1h) . . . . . . . . . . . . . . . 25 table 16. output in 8-bit video port format (register vp_ctrl address = 98h) . . . . . . . . . . . . . . . . 26 table 17. example of supported video formats . . . . . . . 27 table 18. examples of 3d video formats timing supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 19. snpb eutectic process (from j-std-020c) . . . 33 table 20. lead-free process (from j-std-020c) . . . . . . 33 table 21. abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 22. revision history . . . . . . . . . . . . . . . . . . . . . . . . 36 23. figures fig 1. block diagram of tda19977a; TDA19977B . . . . .5 fig 2. pin configuration for tda19977a; TDA19977B. . .6 fig 3. an example of an application with edid memory shared over all three hdmi inputs . . . . .16 fig 4. an example of an application with edid memory shared over two hdmi inputs. . . . . . . . .17 fig 5. output timing diagram pin vclk on pins vp[29:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 fig 6. output timing diagram pin aclk on pins ap[5:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 fig 7. application diagram of tda19977a; TDA19977B . . . . . . . . . . . . . . . . . .30 fig 8. package outline sot612-3 (hlqfp144) . . . . . .31 fig 9. temperature profiles for large and small components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 www.datasheet.in
nxp semiconductors tda19977a; TDA19977B triple input hdmi receiver interface with digital processing ? nxp b.v. 2010. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 19 november 2010 document identifier: tda19977a_TDA19977B please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 24. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 2 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 quick reference data . . . . . . . . . . . . . . . . . . . . . 3 5 ordering information . . . . . . . . . . . . . . . . . . . . . 4 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 6 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 functional description . . . . . . . . . . . . . . . . . . 10 8.1 software drivers . . . . . . . . . . . . . . . . . . . . . . . 10 8.2 hdmi inputs . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8.3 termination resistance control . . . . . . . . . . . . 10 8.4 equalizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8.5 activity detection. . . . . . . . . . . . . . . . . . . . . . . 11 8.6 high-bandwidth digital content protection (tda19977a only) . . . . . . . . . . . . . . . . . . . . . 11 8.7 color depth unpacking . . . . . . . . . . . . . . . . . . 11 8.8 derepeater . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8.9 upsample . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8.10 packet extraction . . . . . . . . . . . . . . . . . . . . . . 12 8.11 audio pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8.12 audio formatter . . . . . . . . . . . . . . . . . . . . . . . . 12 8.13 sync timing measurement . . . . . . . . . . . . . . . 14 8.14 format measurement timing. . . . . . . . . . . . . . 14 8.15 color space conversion . . . . . . . . . . . . . . . . . 14 8.16 4:2:2 downsampling filters . . . . . . . . . . . . . . . 14 8.17 range control . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.18 dithering function . . . . . . . . . . . . . . . . . . . . . . 14 8.19 4:2:2 formatter . . . . . . . . . . . . . . . . . . . . . . . . 15 8.20 video port selection . . . . . . . . . . . . . . . . . . . . 15 8.21 output buffers . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.22 vhref timing generator . . . . . . . . . . . . . . . . 15 8.23 i 2 c-bus serial interface . . . . . . . . . . . . . . . . . . 15 8.24 power management . . . . . . . . . . . . . . . . . . . . 16 8.25 edid memory management . . . . . . . . . . . . . . 16 8.25.1 edid memory shared over all three hdmi inputs . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.25.2 edid memory shared over two hdmi inputs . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9 i 2 c-bus protocol. . . . . . . . . . . . . . . . . . . . . . . . 17 10 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17 11 thermal characteristics . . . . . . . . . . . . . . . . . 18 12 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 18 13 output video port formats. . . . . . . . . . . . . . . . 21 14 example of supported video formats . . . . . . 27 15 application information . . . . . . . . . . . . . . . . . 30 16 package outline. . . . . . . . . . . . . . . . . . . . . . . . 31 17 soldering of smd packages . . . . . . . . . . . . . . 32 17.1 introduction to soldering. . . . . . . . . . . . . . . . . 32 17.2 wave and reflow soldering. . . . . . . . . . . . . . . 32 17.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . 32 17.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . 33 18 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 35 19 revision history . . . . . . . . . . . . . . . . . . . . . . . 36 20 legal information . . . . . . . . . . . . . . . . . . . . . . 37 20.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 37 20.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 20.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 37 20.4 licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 20.5 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 38 21 contact information . . . . . . . . . . . . . . . . . . . . 38 22 tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 23 figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 24 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 www.datasheet.in

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